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Espressif Systems /ESP32-C3 /SYSTEM /SYSCLK_CONF

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Interpret as SYSCLK_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PRE_DIV_CNT0SOC_CLK_SEL 0CLK_XTAL_FREQ0 (CLK_DIV_EN)CLK_DIV_EN

Description

system clock config register

Fields

PRE_DIV_CNT

reg_pre_div_cnt
SOC_CLK_SEL

reg_soc_clk_sel
CLK_XTAL_FREQ

reg_clk_xtal_freq
CLK_DIV_EN

reg_clk_div_en

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data